For manufacturing a multilevel circuit board having fine interconnects with a line width of 20 μm and a pattern pitch of 20 μm, a wide variety of plating methods have so far been proposed. A semi-additive method, as typical of these methods, is such a method in which a circuit board is subjected to electroless copper plating as a substrate for electrical copper plating in forming a copper circuit. A circuit pattern is then formed by a resist and the copper circuit is formed by electrical copper plating.
However, with this semi-additive method, the following problem arises as the line width or the pattern pitch becomes finer. That is, misregistration or development defects tend to be produced as a result of formation of the resist, thus possibly producing line breakage or circuit shorting. In addition, the electroless copper plating formed as a substrate for current conduction for electrical copper plating needs to be removed by etching after the processing for electrical copper plating. However, this etching process may give breakage of useful circuit portions or circuit shorting due to insufficient etching.
Another typical method is a full-additive method. With this full-additive method, a catalyst is initially afforded to a circuit board in which vias have already been opened. A circuit pattern then is formed by a resist and a copper circuit is formed solely by electroless copper plating.
However, even with this full additive method, the following problems arise with further refinement of the line width or the pattern pitch. That is, misregistration or development defects tend to be produced as a result of formation of the resist, thus possibly producing line breakage or circuit shorting. In addition, the catalyst is left below the resist by reason of process-related constraints. There are cases where the insulation performance between the circuits tends to be lowered due to the catalyst left, thus possibly leading to shorting with refinement of the circuit pattern.
To overcome the above-mentioned deficiency, such a method is tentatively used in which a trench or a via is formed in a board surface using the laser and the trench or the via thus formed is filled with plating copper by electroless copper plating.
However, the technique used so far in filling the trench or the via by electroless plating is aimed to fabricate a circuit on a wafer having a trench or a via of a diameter or a width equal to 1 μm (=1000 nm) or less. However, a larger trench or via of a diameter or a width equal to several to one hundred and tens of μm, such as is used in a printed circuit board, cannot be filled sufficiently with plating metal by using this technique.
With the electroless plating solution currently used for vias, plating metal can be deposited by increasing the plating thickness. However, in this case, gaps (voids or seams) tend to be produced below the opening part of the via, thus possibly causing line breakages, etc.
A sulfur-based compound so far used in the conventional technique for suppression of voids or seams is contained in a solution for electroplating of acidic copper sulfate used until now for field via plating or dual copper damascene. If the compound is used in a highly alkaline electroless plating solution, it is destabilized and tends to undergo self-decomposition. That is, the compound is unable to remain in a stabilized operating state for prolonged time and hence is not practically useful (see Patent Publications 1 and 2).    [Patent Publication 1] Japanese Patent Application Laid-Open No. 2000-80494    [Patent Publication 2] International Publication No. WO5/028088